C502 can receives following several signal entered: a is in the put integration HF head output of TV video signal TUNER_CVBS, the signal entered to IC502 Hou, by A/D conversion, and video decoding Hou, decoding out digital video signal; II is s Terminal, and AV interface output of simulation video signal, the signal entered to IC502 Hou, by AfD conversion, and video decoding Hou, decoding out digital video signal; three is VGA interface, and YPbPr interface output of simulation video signal, After the signal a/d converter, converts digital video signals four IC604 digital video signal output is HDMI receiver chip HDMI_DIN.

Signals above after appropriate treatment, then by a IC502 internal switch channel selection switch select the, and then sent to the deinterlacing, image scaling circuit for processing.

For the convenience of deinterlacing and image zoom for image processing, an image signal needs to be stored, this task consists of frame memory, IC600 and IC601 (EM6A9320BI-5MG) complete, as shown in Figure 11-11.

IC502 via data line DR_MD1 (0:31), address line DDR_MA (0:11) and the line of control (CLKE, CS0, RAS, CAS, and WE and the DDR DQM, DDR_DQS etc) linked with IC600, IC601. IC502 and synergy IC600, IC601, different formats, different resolution interlaced/progressive signals a unified signal converted to fixed resolution line by line, added to internal LVDS circuit internal circuit control, converted to a mixture of LVDS serial data stream, and finally, composed of IC502, TXOUTE0+, TXOUTE0-, TXOUTE1+, and TXOUTE1-, TXOUTE2+, and TXOUTE2-, TXOUTE3+, and TXOUTE3-, TXOUTEC+, and TXOUTEC-and TXOUTO0+ and the TXOUTO0-, TXOUTO1+, and TXOUTO1-, TXOUTO2+, and TXOUTO2-, TXOUT03+, and TXOUTO3-, TXOUTOC+, TXOUTOC--side dual channel 8-bit LVDS signal output through LVDS cable to the LCD Panel receiver.

In addition, inside the IC502 OSD controller contains a complete, without any external components, OSD display can be realized.

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